Espressif Systems /ESP32-C6 /LP_I2C0 /I2C_CTR

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Interpret as I2C_CTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (I2C_SDA_FORCE_OUT)I2C_SDA_FORCE_OUT 0 (I2C_SCL_FORCE_OUT)I2C_SCL_FORCE_OUT 0 (I2C_SAMPLE_SCL_LEVEL)I2C_SAMPLE_SCL_LEVEL 0 (I2C_RX_FULL_ACK_LEVEL)I2C_RX_FULL_ACK_LEVEL 0 (I2C_TRANS_START)I2C_TRANS_START 0 (I2C_TX_LSB_FIRST)I2C_TX_LSB_FIRST 0 (I2C_RX_LSB_FIRST)I2C_RX_LSB_FIRST 0 (I2C_CLK_EN)I2C_CLK_EN 0 (I2C_ARBITRATION_EN)I2C_ARBITRATION_EN 0 (I2C_FSM_RST)I2C_FSM_RST 0 (I2C_CONF_UPGATE)I2C_CONF_UPGATE

Description

Transmission setting

Fields

I2C_SDA_FORCE_OUT

1: direct output, 0: open drain output.

I2C_SCL_FORCE_OUT

1: direct output, 0: open drain output.

I2C_SAMPLE_SCL_LEVEL

This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level.

I2C_RX_FULL_ACK_LEVEL

This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.

I2C_TRANS_START

Set this bit to start sending the data in txfifo.

I2C_TX_LSB_FIRST

This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit.

I2C_RX_LSB_FIRST

This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit.

I2C_CLK_EN

Reserved

I2C_ARBITRATION_EN

This is the enable bit for arbitration_lost.

I2C_FSM_RST

This register is used to reset the scl FMS.

I2C_CONF_UPGATE

synchronization bit

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